Field of the Invention
The present invention relates to a method for detecting the reliability of integrated semiconductor components at high temperatures, and in particular, relates to highly accelerated tests for determining the reliability of semiconductor circuits.
A high reliability, in particular in the case of integrated semiconductor circuits, but also in thin-film technology, represents a significant factor in production and later use. Therefore, a multiplicity of tests are carried out during fabrication in order to be able to give as accurate a statement as possible with regard to the quality of a respective product, and also with regard to a respective fabrication process.
Since the structure width in semiconductor circuits is increasingly being reduced with advancing integration density, corresponding structures in large scale integrated circuits are loaded with very high current densities and/or temperatures during operation. In the case of such high current densities and temperatures, a multiplicity of mechanisms can lead to the failure of a respective semiconductor component and thus of the semiconductor circuit.
Such mechanisms are, for example, electromigration, giving rise to a material transport, in particular, in interconnects in the electron direction. Furthermore, instances of high current-density and temperature-dependent stressing can impair or destroy doping regions in a semiconductor substrate on account of barrier degradation or eutectic metal penetration. On the other hand, in field-effect transistor structures, such instances of stressing can also alter the properties of the so-called gate and/or tunnel oxides in a lasting manner, which again results in an adverse effect on the respective semiconductor components. The same applies to capacitances, inductances, memory elements, etc., formed in semiconductor substrates, in which, by way of example, passivation and intermediate dielectric layers can also be altered in a lasting manner by such current-density-, voltage- and/or temperature-dependent stressing and lead to the point of failure of the semiconductor component.
In order to be able to estimate a maximum lifetime of semiconductor circuits or thin-film circuits, a multiplicity of reliability tests are carried out, which preferably take place at elevated temperatures and current densities on specific test structures. These elevated temperatures were usually realized in special furnaces, whereby an accelerated artificial aging process can be brought about. However, since the fabrication of integrated semiconductor circuits, in particular, can last several weeks and checking for possibly defective structures is desired as early as during fabrication or immediately after completion, so-called accelerated and highly accelerated tests have been developed which enable a deviation in the fabrication in regular inspection measurements. In this case, these measurements must proceed is in a range of seconds in order not to increase the fabrication time and thus the fabrication costs of respective semiconductor circuits.
FIG. 1 shows a device for detecting the reliability of integrated semiconductor components in accordance with the prior art, as is disclosed for example in the reference J. A. Scheideler, et al. “The Systematic Approach to Wafer Level Reliability”, Solid State Technology, March 1995, page 47 et seq.
In accordance with FIG. 1, the MOS transistor, which is an integrated semiconductor component HBE that will be tested or stressed, is situated in a semiconductor substrate 1 that is p−-doped, for example. The semiconductor component HBE is formed in an n-type well 2 of the semiconductor substrate 1 and essentially includes a p+-doped drain region D, an associated contact K1, a p+-doped source region S with an associated contact K2, a gate oxide layer 3 and a gate or a control layer G, which is situated above the gate oxide layer 3 and essentially defines a channel region lying between drain region D and source region S.
In order to check the quality and the process reliability, in the case of a large scale integrated circuit in accordance with FIG. 1, tests are carried out at temperatures above room temperature. Diverse models are used in order to characterize the degradation behavior, and a precise knowledge of the temperature is essential. Therefore, in accordance with FIG. 1, a local heating arrangement or a heating element HE is situated in an insulating layer 4 (SiO2) in direct proximity to the semiconductor component HBE. Damage to the product on account of an external heating arrangement that is otherwise required can thereby be avoided.
In order to detect the temperature of the semiconductor component HBE to be stressed, in accordance with FIG. 1, there is a temperature sensor TS in the form of an aluminum meander that is spaced apart above the insulating layer 4. The linear relationship between the resistance and the temperature of the metal interconnect is evaluated.
What is disadvantageous, however, in the case of such a device for detecting the reliability of an integrated semiconductor component is that the distance between the structure that will be tested or the semiconductor component HBE and the temperature sensor or the aluminum meander TS is large and in between there lies one or a plurality of insulating intermediate layers 4 which constitute a large thermal resistance. As a result, a sufficiently accurate and direct statement with regard to the temperature present at the relevant region of the structure being tested or of the semiconductor component HBE is not possible. Furthermore, at higher temperatures, degradation of the aluminum or of the temperature sensor TS also occurs, for which reason, an exact and reproducible temperature determination is no longer possible after relatively long stress. As a further disadvantage of this conventional device, mention may be made of the extraordinarily high space requirement/contact area requirement, which essentially results from a 4-point resistance measurement and the pads required therefore.
Furthermore, the literature reference Gerard C. M. Mejer, “Thermal Sensors Based on Transistors”, Sensors and Actuators, 10 (1986) 103-125 discloses utilizing the temperature dependence of a bipolar transistor or of its base-emitter voltage for realizing a temperature sensor.